Field of the Invention
The present invention relates to video decoders. More particularly, this invention relates to video decoders configured to perform inverse transform operations as part of their decoding operations.
Description of the Prior Art
A contemporary video decoder may be required to perform video decoding operations in accordance with a number of video standards, such as MPEG2, MPEG4, H.263, H.264 high profile, VP8, VC-1 and so on. It is known that a particularly computationally intensive part of the video decoding process is the inverse transform operation (often implemented as an inverse discrete cosine transform).
Video decoding is typically performed on the basis of 8×8 blocks of pixel data, wherein four 8×8 blocks of luma (Y) data and two 8×8 blocks of chroma (Cb and Cr) data represent a given macroblock of the video data. The inverse transform operation is performed on all six 8×8 blocks for each macroblock to produce six inverse transformed output 8×8 blocks. The inverse transform on an 8×8 block of values may be implemented as one 8×8 transform, two 8×4/4×8 transforms or four 4×4 transforms, the choice between these options being defined on a macroblock-by-macroblock basis. Accordingly, if six 8×8 blocks are typically handled by the inverse transform process for each macroblock of the encoded video, wherein each 8×8 block must be subjected to one of four different inverse transform configurations (8×8; 8×4; 4×8 or 4×4), and the particular inverse transform operation is defined in accordance with the particular video standard used to encode the current frame of video data, it will be appreciated that a great number and variety of operations are needed to be performed as part of the inverse transform process. Furthermore it is common for a contemporary video standard to require a conformant video decoder to provide a bit-exact implementation of the inverse discrete cosine transformation (IDCT), and hence a contemporary multi-standard video decoder is required to be able to perform a considerable range operations in order to implement the inverse transform process. Providing the capability to handle the number and variety of operations required to perform the inverse transform thus represents a significant design challenge.
One approach to providing a video decoder able to perform the inverse transform operations required by a range of video standards is for the inverse transform operation to be performed by software (for example on a DSP or general purpose processor). Whilst this common technique has the advantage that new video standards or developments to existing standards can be handled by appropriate updating of the software, on the other hand a relatively large and powerful processor is required to provide sufficient performance for contemporary video (e.g. high definition (HD) video at 1080p30), which can consume both considerable power and silicon area.
Alternatively, a more hardware-based approach may be taken to the provision of the required inverse transform processing, but although it may be possible to share some of the hardware required for performing the inverse transform operations for each standard, an extensive amount of circuitry may still be required to provide the inverse transform operations for each standard. Moreover a hardware-based approach is liable to lack flexibility for supporting new or developing standards. For example, “A Low-Cost Very Large Scale Integration Architecture for Multistandard Inverse Transform”, Honggang Qi, Qingming Huang and Wen Gao, IEEE Transactions on Circuits and Systems II: Express Briefs, July 2010, Vol. 57 Issue 7, pp. 551-555 concentrates on sharing circuits between the different video standards at the circuit level. Alternatively, “A highly efficient inverse transform architecture for multi-standard HDTV decoder”, Hang Zhang, Peilin Liu, Yu Hong, Dajiang Zhou and Satoshi Goto, IEEE 8th International Conference on ASIC, 2009, October 2009, pp. 525-528 uses an approach based on tables to provide some configurability to the linear inverse transform operations. However, in practice not all transforms are linear.
Accordingly, it would be desirable to provide an improved technique for enabling the inverse transform operations to be performed within a video decoder, which retained the flexibility and adaptability of a software-based approach, whilst also being provided within a relatively small and efficient hardware unit.